1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a dynamic random access memory (DRAM) and particularly to a dynamic RAM having an improved bit-line sense amplifier.
2. Description of the Related Art
A semiconductor memory device, such as a dynamic RAM, comprising memory cell arrays of, for example, one transistor and one capacitor, provides a sense amplifier (S/A) to amplify data from a bit line and transfer the amplified data to an output line. Data of each memory cell is read out through bit lines. However, the capacity of the bit lines is larger than that of the memory cell, so the sense amplifier must be highly sensitive to detect the data of "H" or "L".
A structure of a conventional bit line sense amplifier circuit 4 using a gate input type sense amplifier (S/A) 6 is shown in FIGS. 1(a) and 1(b). As shown in FIG. 1(a), a pair of bit lines BL,/BL is precharged to a voltage of (1/2) Vcc by a (1/2) Vcc generator 8 during a precharge operation and a sensing operation is set to be in a floating state. The sense amplifier 6 has at least two transistors and a bit line voltage is applied to a gate of respective ones of the transistors.
After these operations, a reading out operation is carried out by selecting a desired word line as shown in FIG. 1(b).
FIG. 2 shows a timing chart of each signal in the conventional bit line sense operation explained above. When a control signal /RAS is at an "H" level, (i.e., in a state of precharge), a switch EQ1 in FIG. 1(a) is turned on "ON" and a pair of bit lines BL,/BL is precharged to (1/2) Vcc. The signal /RAS is provided as a row address strobe signal. Data of a selected memory cell (MC) is read out to bit line BL, by setting a word line (WL), which is connected to a gate of the selected memory cell, to be "H" level. A change in potential of a pair of bit lines BL,/BL is sensed by the sense amplifier 6 and is read out to output lines OUT,/OUT.
The sense amplified 6, which receives a bit line voltage at the gate of the transistor in the sense amplifier, cannot amplify the bit line voltage by itself, so a flip-flop (F/F) type sense amplifier is attached in parallel.
However, in the conventional structure of the sense amplifier circuit, which uses conventional operational timing, when a pair of bit lines BL,/BL is precharged to (1/2) Vcc, if a pair of transistors of the sense amplifier circuit has an imbalance in a threshold voltage or a channel conductance, the ability of the sense amplifier circuit to amplify decreases and either a time for reading out data of a bit line increases or an error signal is output. Also, when such an imbalance occurs, more deviations in read out time occur among the sense amplifier circuits in the memory device.
Thus, conventional sense amplifier circuits have a problem in that they generate an input-offset voltage by the imbalance of the threshold voltage or channel conductance of the pair of transistors in the sense amplifier. This imbalance decreases the performance quality of the sense amplifier circuit.